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Disambiguation of "Kudva, Sudhir S."

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Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks.

, , , , , and . ASYNC, page 75-82. IEEE Computer Society, (2016)

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S. Schumann

S. Seemann

S. Wartzack

Boettinger S

S. Toro

 

Other publications of authors with the same name

A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2019)Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects., , , , , , , , , and 6 other author(s). CICC, page 1-8. IEEE, (2018)A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator., , , , , , , , , and 3 other author(s). J. Solid-State Circuits, 54 (1): 43-54 (2019)Fully integrated on-chip DC-DC converter with a 450x output range., and . CICC, page 1-4. IEEE, (2010)A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator., , , , , , , , , and 3 other author(s). ISSCC, page 276-278. IEEE, (2018)A Low Power Frequency Multiplication Technique for ZigBee Transciever., , and . VLSI Design, page 150-155. IEEE Computer Society, (2007)Fully integrated capacitive converter with all digital ripple mitigation., and . CICC, page 1-4. IEEE, (2012)Fully-Integrated On-Chip DC-DC Converter With a 450X Output Range., and . J. Solid-State Circuits, 46 (8): 1940-1951 (2011)Fully Integrated Capacitive DC-DC Converter With All-Digital Ripple Mitigation Technique., and . J. Solid-State Circuits, 48 (8): 1910-1920 (2013)High power-density, hybrid inductive/capacitive converter with area reuse for multi-domain DVS., , and . CICC, page 1-4. IEEE, (2014)