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Disambiguation of "Calhoun, Benton H."

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Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks.

, , , , , and . ASYNC, page 75-82. IEEE Computer Society, (2016)

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H. Binz

H. Bungartz

H. Binz

H. Binz

H. J. Dennig

 

Other publications of authors with the same name

Nonrandom Device Mismatch Considerations in Nanoscale SRAM., , , and . IEEE Trans. VLSI Syst., 20 (7): 1211-1220 (2012)A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node., , , and . VLSI Design, page 72-75. IEEE Computer Society, (2013)Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems., , , , , , and . FCCM, page 236. IEEE Computer Society, (2014)Improving SRAM Vmin and yield by using variation-aware BTI stress., , , , , and . CICC, page 1-4. IEEE, (2010)Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write VMIN., , , and . DATE, page 1819-1824. EDA Consortium San Jose, CA, USA / ACM DL, (2013)A 10 mV-Input Boost Converter With Inductor Peak Current Control and Zero Detection for Thermoelectric and Solar Energy Harvesting With 220 mV Cold-Start and -14.5 dBm, 915 MHz RF Kick-Start., , , , and . J. Solid-State Circuits, 50 (8): 1820-1832 (2015)A 32 b 90 nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation From Sub-Threshold to High Performance., , , , , and . J. Solid-State Circuits, 49 (2): 545-552 (2014)Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (12): 1908-1920 (2010)Modeling SRAM dynamic VMIN., , , and . ICICDT, page 1-4. IEEE, (2014)Optimizing SRAM bitcell reliability and energy for IoT applications., , and . ISQED, page 12-17. IEEE, (2016)