Autor der Publikation

Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write VMIN.

, , , und . DATE, Seite 1819-1824. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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Dr. Robert Löw University of Stuttgart

Replication Data for: Highly efficient real-time spatially resolved sensing of ultraviolet light, , , , , , , und . Dataset, (2025)Related to: Yannick Schellander, Fabian Munkes, Alexander Trachtmann, Patrick Schalberger, Robert Löw, Harald Kübler, Tilman Pfau, Norbert Fruehauf, "Highly efficient real-time spatially resolved sensing of ultraviolet light," Proc. SPIE 13109, Metamaterials, Metadevices, and Metasystems 2024, 1310906 (2024). doi: 10.1117/12.3028038.
Replication Data for: Highly efficient real-time spatially resolved sensing of ultraviolet light, , , , , , , und . Dataset, (2025)Related to: Yannick Schellander, Fabian Munkes, Alexander Trachtmann, Patrick Schalberger, Robert Löw, Harald Kübler, Tilman Pfau, Norbert Fruehauf, "Highly efficient real-time spatially resolved sensing of ultraviolet light," Proc. SPIE 13109, Metamaterials, Metadevices, and Metasystems 2024, 1310906 (2024). doi: 10.1117/12.3028038.Replication Data for: Ultraviolet Photodetectors and their Readout Realization for Future Active-Matrix Sensing, , , , , , , und . Dataset, (2025)Related to: Y. Schellander, M. Schamber, F. Munkes, R. Loew, P. Schalberger, H. Kübler, T. Pfau, and N. Fruehauf, “Ultraviolet photodetectors and their readout realization for future active-matrix sensing”, Proceedings of the International Display Workshops,30 (2023), 151-154. doi: 10.36463/idw.2023.0151.
 

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Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience., , , und . IEEE Trans. Computers, 63 (2): 497-509 (2014)DFX and Productivity.. VLSI Design, Seite 8. IEEE Computer Society, (2009)Low-power design tools: are EDA vendors taking this matter seriously?, , , , , und . DATE, Seite 1227. European Design and Automation Association, Leuven, Belgium, (2006)Analytical model for SRAM dynamic write-ability degradation due to gate oxide breakdown., und . DATE, Seite 1172-1175. IEEE, (2011)Noise and reliability containment approaches., und . CICC, Seite 20-21. IEEE, (2005)Trends in SLI design and their effect on test., und . ITC, Seite 628-637. IEEE Computer Society, (1999)Current ratios: a self-scaling technique for production IDDQ testing., , , , , , und . ITC, Seite 1148-1156. IEEE Computer Society, (2000)Applying Defect-Based Test to Embedded Memories in a COT Model.. MTDT, Seite 72-. IEEE Computer Society, (2003)Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation., , , , und . ISQED, Seite 139-146. IEEE, (2010)ITC 2003: Breaking Test Interface Bottlenecks., und . IEEE Design & Test of Computers, 20 (5): 54- (2003)