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Disambiguation of "Wei, Gu-Yeon"

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A High-Throughput Maximum a posteriori Probability Detector.

, , and . CICC, page 455-458. IEEE, (2007)

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Wei Yu University of Stuttgart

Do Yeon Kim University of Stuttgart

Li-Wei Chen University of Stuttgart

Yasemin Gündüz University of Stuttgart

Yanan Guo University of Stuttgart

 

Other publications of authors with the same name

Digital wireline and PLL techniques., and . CICC, IEEE, (2009)A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction., , and . CICC, page 459-462. IEEE, (2008)Process Variation Tolerant 3T1D-Based Cache Architectures., , , and . MICRO, page 15-26. IEEE Computer Society, (2007)Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling., , , , , , and . MICRO, page 77-88. IEEE Computer Society, (2010)Understanding voltage variations in chip multiprocessors using a distributed power-delivery network., , , , and . DATE, page 624-629. EDA Consortium, San Jose, CA, USA, (2007)A Wide Dynamic Range Sparse FC-DNN Processor with Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET., , , , , and . ESSCIRC, page 158-161. IEEE, (2018)A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance., , , and . J. Solid-State Circuits, 43 (4): 855-863 (2008)An 8×5 Gb/s Parallel Receiver With Collaborative Timing Recovery., , , and . J. Solid-State Circuits, 44 (11): 3120-3130 (2009)DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications., , , and . J. Solid-State Circuits, 53 (9): 2722-2731 (2018)Assisting High-Level Synthesis Improve SpMV Benchmark Through Dynamic Dependence Analysis., , , , and . IEEE Trans. on Circuits and Systems, 65-II (10): 1440-1444 (2018)