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Disambiguation of "Wei, Gu-Yeon"

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Process Variation Tolerant 3T1D-Based Cache Architectures.

, , , and . MICRO, page 15-26. IEEE Computer Society, (2007)

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Wei Yu University of Stuttgart

Junyuan Gu University of Stuttgart

Dr. rer. nat. Ran Wei University of Stuttgart

Wei Zhang University of Stuttgart

Li-Wei Chen University of Stuttgart

 

Other publications of authors with the same name

Process Variation Tolerant 3T1D-Based Cache Architectures., , , and . MICRO, page 15-26. IEEE Computer Society, (2007)Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling., , , , , , and . MICRO, page 77-88. IEEE Computer Society, (2010)Digital wireline and PLL techniques., and . CICC, IEEE, (2009)A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction., , and . CICC, page 459-462. IEEE, (2008)Understanding voltage variations in chip multiprocessors using a distributed power-delivery network., , , , and . DATE, page 624-629. EDA Consortium, San Jose, CA, USA, (2007)On-chip deep neural network storage with multi-level eNVM., , , , , and . DAC, page 169:1-169:6. ACM, (2018)The HELIX project: overview and directions., , , , and . DAC, page 277-282. ACM, (2012)Assisting High-Level Synthesis Improve SpMV Benchmark Through Dynamic Dependence Analysis., , , , and . IEEE Trans. on Circuits and Systems, 65-II (10): 1440-1444 (2018)A Wide Dynamic Range Sparse FC-DNN Processor with Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET., , , , , and . ESSCIRC, page 158-161. IEEE, (2018)Network Pruning for Low-Rank Binary Indexing., , , , and . CoRR, (2019)