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Disambiguation of "Masu, Kazuya"

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LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process.

, , , , and . ASP-DAC, page 97-98. IEEE, (2008)

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Other publications of authors with the same name

A 0.5-V 5.8-GHz low-power asymmetrical QPSK/OOK transceiver for wireless sensor network., , , , , , , , , and . ASP-DAC, page 40-41. IEEE, (2015)Via Distribution Model for Yield Estimation., , and . ISQED, page 479-484. IEEE Computer Society, (2006)A 0.5-V 2.5-GHz high-gain low-power regenerative amplifier based on Colpitts oscillator topology in 65-nm CMOS., , , , , and . APCCAS, page 340-343. IEEE, (2014)A Variability-Aware Adaptive Test Flow for Test Quality Improvement., , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (7): 1056-1066 (2014)Determination of optimal polynomial regression function to decompose on-die systematic and random variations., , , and . ASP-DAC, page 518-523. IEEE, (2008)A 950μW 5.5-GHz low voltage PLL with digitally-calibrated ILFD and linearized varactor., , , , , and . ASP-DAC, page 23-24. IEEE, (2014)An 8.865-GHz -244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique., , , , , , , , , and 3 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)An ultra-low-power RF transceiver with a 1.5-pJ/bit maximally-digital impulse-transmitter and an 89.5-μW super-regenerative RSSI., , , , , , , and . A-SSCC, page 265-268. IEEE, (2014)Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis., , , and . IEICE Transactions, 97-C (4): 280-288 (2014)A Sub-1mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65nm CMOS., , , , , and . IEICE Transactions, 97-C (6): 495-504 (2014)