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Disambiguation of "Shintani, Michihiro"

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A Variability-Aware Adaptive Test Flow for Test Quality Improvement.

, , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (7): 1056-1066 (2014)

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Other publications of authors with the same name

An Adaptive Test for Parametric Faults Based on Statistical Timing Information., , , , , , , and . Asian Test Symposium, page 151-156. IEEE Computer Society, (2009)Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control., , , , , and . ATS, page 234-239. IEEE Computer Society, (2016)Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation., , , , , and . ACM Great Lakes Symposium on VLSI, page 203-208. ACM, (2016)Decimal Multiplication Using Combination of Software and Hardware., , and . APCCAS, page 239-242. IEEE, (2018)Sensorless estimation of global device-parameters based on Fmax testing., and . ICCAD, page 498-503. IEEE, (2014)Huffman-Based Test Response Coding., , and . IEICE Transactions, 88-D (1): 158-161 (2005)Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing., , , , and . J. Electronic Testing, 32 (5): 601-609 (2016)Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability., , , and . IEICE Transactions, 99-A (7): 1400-1409 (2016)Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation., , , , and . IEICE Transactions, 100-A (7): 1464-1472 (2017)A Variability-Aware Adaptive Test Flow for Test Quality Improvement., , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (7): 1056-1066 (2014)