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A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.

, , , , and . ISLPED, page 8-13. ACM, (2007)

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Corrections to "Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction"., and . IEEE Trans. VLSI Syst., 23 (7): 1380 (2015)Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction., , , , , , , , , and 2 other author(s). IEEE Trans. VLSI Syst., 23 (3): 534-543 (2015)Robust bias temperature instability refresh design and methodology for memory cell recovery., , , , and . ICICDT, page 1-4. IEEE, (2014)Critical evaluation of SOI design guidelines., and . IEEE Trans. VLSI Syst., 12 (9): 885-894 (2004)Efficient analog circuit optimization using sparse regression and error margining., , , , and . ISQED, page 410-415. IEEE, (2016)Automated FPGA implementations of BIP designs., , , , and . SIES, page 165-170. IEEE, (2016)Yield estimation of SRAM circuits using "Virtual SRAM Fab"., , , , , , , , , and 2 other author(s). ICCAD, page 631-636. ACM, (2009)Data Imbalance Handling Approaches for Accurate Statistical Modeling and Yield Analysis of Memory Designs., , and . ISCAS, page 1-5. IEEE, (2019)Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives., , and . ISLPED, page 337-342. ACM, (2010)A Disturb Decoupled Column Select 8T SRAM Cell., , and . CICC, page 25-28. IEEE, (2007)