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Electrothermal model for simulation of bulk-Si and SOI diodes in ESD protection circuits., , , and . Microelectronics Reliability, 41 (11): 1781-1787 (2001)An 8-mW, ESD-protected, CMOS LNA for Ultra-Wideband Applications., , and . CICC, page 385-388. IEEE, (2006)Full-Component Modeling and Simulation of Charged Device Model ESD., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (7): 1105-1113 (2016)Simulator-independent compact modeling of vertical npn transistors for ESD and RF circuit simulation., and . Microelectronics Reliability, 43 (7): 1021-1027 (2003)FEC-based 4 Gb/s backplane transceiver in 90nm CMOS., , , , , , , and . CICC, page 1-4. IEEE, (2012)CDM-ESD induced damage in components using stacked-die packaging., , , and . CICC, page 1-4. IEEE, (2011)UVeriESD: An ESD verification tool for SoC design., , , and . APCCAS, page 53-56. IEEE, (2008)Improved GGSCR layout for overshoot reduction., , , and . IRPS, page 3. IEEE, (2015)Critical evaluation of SOI design guidelines., and . IEEE Trans. VLSI Syst., 12 (9): 885-894 (2004)Compact distributed multi-finger MOSFET model for circuit-level ESD simulation., , and . Microelectronics Reliability, (2016)