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Disambiguation of "Chuang, Ching-Te"

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A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.

, , , , and . ISLPED, page 8-13. ACM, (2007)

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Dipl.-Ing. Philipp Tempel

Kinematics and dynamics modeling for real-time simulation of the cable-driven parallel robot IPAnema 3, , and . Proceedings of the 14th IFToMM World Congress, page 117-123. Taipei, IFToMM, (2015)

Dr. rer. nat. Attila Teleki University of Stuttgart

Dr. -Ing. Kristina Terheiden University of Stuttgart

Marco Testa University of Stuttgart

 

Other publications of authors with the same name

40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist., , , , , , and . IEEE Trans. on Circuits and Systems, 61-I (9): 2578-2585 (2014)Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist., , , , and . IEEE Trans. on Circuits and Systems, 57-I (12): 3039-3047 (2010)Reducing parasitic BJT effects in partially depleted SOI digital logic circuits., , and . Microelectronics Journal, 39 (2): 275-285 (2008)A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control., , , , , , , , , and 9 other author(s). SoCC, page 197-200. IEEE, (2011)SOI Digital Circuits: Design Issues., and . VLSI Design, page 474-479. IEEE Computer Society, (2000)All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction., , , , , , and . VLSI-DAT, page 1-4. IEEE, (2015)On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits., , , and . ISQED, page 815-820. IEEE Computer Society, (2008)Testing strategies for a 9T sub-threshold SRAM., , , , , , and . ITC, page 1-10. IEEE Computer Society, (2012)A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line., , , , , , and . Microelectronics Journal, (2016)Self-Repairing SRAM Using On-Chip Detection and Compensation., , , , and . IEEE Trans. VLSI Syst., 18 (1): 75-84 (2010)