%0 Conference Paper %1 conf/vlsi-dat/KuoHWLCCH15 %A Kuo, Yi-Ping %A Huang, Po-Tsang %A Wu, Chung-Shiang %A Liang, Yu-Jie %A Chuang, Ching-Te %A Chu, Yuan-Hua %A Hwang, Wei %B VLSI-DAT %D 2015 %I IEEE %K dblp %P 1-4 %T All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. %U http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2015.html#KuoHWLCCH15 %@ 978-1-4799-6275-4

@inproceedings{conf/vlsi-dat/KuoHWLCCH15, added-at = {2015-09-28T00:00:00.000+0200}, author = {Kuo, Yi-Ping and Huang, Po-Tsang and Wu, Chung-Shiang and Liang, Yu-Jie and Chuang, Ching-Te and Chu, Yuan-Hua and Hwang, Wei}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/250d27a71389bbd3371e4383faadf3dc1/dblp}, booktitle = {VLSI-DAT}, crossref = {conf/vlsi-dat/2015}, ee = {http://dx.doi.org/10.1109/VLSI-DAT.2015.7114514}, interhash = {ff8b7a56286bd142b5e2dcb6c5b7245e}, intrahash = {50d27a71389bbd3371e4383faadf3dc1}, isbn = {978-1-4799-6275-4}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2016-02-02T13:08:57.000+0100}, title = {All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction.}, url = {http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2015.html#KuoHWLCCH15}, year = 2015 }