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Disambiguation of "Hook, Terence"

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Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction.

, , , , , , , , , , , and . IEEE Trans. VLSI Syst., 23 (3): 534-543 (2015)

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Other publications of authors with the same name

Scalability of planar FDSOI and FinFETs and What's in store for the future beyond that?, and . ESSDERC, page 160-163. IEEE, (2015)Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction., , , , , , , , , and 2 other author(s). IEEE Trans. VLSI Syst., 23 (3): 534-543 (2015)Plasma process-induced damage on thick (6.8 nm) and thin (3.5 nm) gate oxide: parametric shifts, hot-carrier response, and dielectric integrity degradation., , and . Microelectronics Reliability, 41 (5): 751-765 (2001)Ultralow-power SRAM technology., , , , , , , , , and 12 other author(s). IBM Journal of Research and Development, 47 (5-6): 553-566 (2003)Enchanced multi-threshold (MTCMOS) circuits using variable well bias., , , , , and . ISLPED, page 165-169. ACM, (2001)Negative bias temperature instability on three oxide thicknesses (1.4/2.2/5.2 nm) with nitridation variations and deuteration., , , , , and . Microelectronics Reliability, 45 (1): 47-56 (2005)Nitrided gate oxides for 3.3-V logic application: Reliability and device design considerations., , and . IBM Journal of Research and Development, 43 (3): 393-406 (1999)Automatic extraction of circuit models from layout artwork for a BiCMOS technology.. IEEE Trans. on CAD of Integrated Circuits and Systems, 11 (6): 732-738 (1992)Fully depleted devices for designers: FDSOI and FinFETs.. CICC, page 1-7. IEEE, (2012)