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Disambiguation of "Bhoj, Ajay N."

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Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction.

, , , , , , , , , , , and . IEEE Trans. VLSI Syst., 23 (3): 534-543 (2015)

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Chinmay Ajay Pabshettiwar University of Stuttgart

Jan-Philipp Negel

Thin-disk multipass amplifier for fs pulses delivering 400 W of average and 2.0 GW of peak power for linear polarization as well as 235 W and 1.2 GW for radial polarization, , , , , , , and . Applied Physics. B, Lasers and optics, 123 (5): 156 (2017)

Michael Neubauer University of Stuttgart

Domänenspezifische Sprache : Automatisierte Echtzeit-Orchestrierung Container-basierter Steuerungsanwendungen, , and . SPS-Magazin, (2024)

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Alexander Naubert

 

Other publications of authors with the same name

Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction., , , , , , , , , and 2 other author(s). IEEE Trans. VLSI Syst., 23 (3): 534-543 (2015)Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology., and . ISQED, page 695-702. IEEE, (2011)Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (1): 47-58 (2013)Pragmatic design of gated-diode FinFET DRAMs., and . ICCD, page 390-397. IEEE Computer Society, (2009)Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs., and . IEEE Trans. VLSI Syst., 22 (3): 548-561 (2014)Design of Efficient Content Addressable Memories in High-Performance FinFET Technology., , and . IEEE Trans. VLSI Syst., 23 (5): 963-967 (2015)Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology., and . IEEE Trans. VLSI Syst., 21 (11): 1975-1988 (2013)3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits., , and . IEEE Trans. VLSI Syst., 21 (11): 2094-2105 (2013)Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism., , , and . VLSI Design, page 300-305. IEEE Computer Society, (2016)Die-level leakage power analysis of FinFET circuits considering process variations., , and . ISQED, page 347-355. IEEE, (2010)