%0 Conference Paper %1 conf/vlsid/ChaudhuriBBJ16 %A Chaudhuri, Sourindra %A Bhoj, Ajay N. %A Bhattacharya, Debajit %A Jha, Niraj K. %B VLSI Design %D 2016 %I IEEE Computer Society %K dblp %P 300-305 %T Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2016.html#ChaudhuriBBJ16 %@ 978-1-4673-8700-2

@inproceedings{conf/vlsid/ChaudhuriBBJ16, added-at = {2016-03-21T00:00:00.000+0100}, author = {Chaudhuri, Sourindra and Bhoj, Ajay N. and Bhattacharya, Debajit and Jha, Niraj K.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2148e79ac2efa365daa879803896fcf8d/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2016}, ee = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2016.34}, interhash = {08f5504a3b83f86770017d9a3e9afbcb}, intrahash = {148e79ac2efa365daa879803896fcf8d}, isbn = {978-1-4673-8700-2}, keywords = {dblp}, pages = {300-305}, publisher = {IEEE Computer Society}, timestamp = {2016-03-22T10:34:40.000+0100}, title = {Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2016.html#ChaudhuriBBJ16}, year = 2016 }