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Disambiguation of "Jha, Niraj K."

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Design of Efficient Content Addressable Memories in High-Performance FinFET Technology.

, , and . IEEE Trans. VLSI Syst., 23 (5): 963-967 (2015)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Dr. Abhinav Jha University of Stuttgart

K. Stahl

K. Lindow

K. Gaiser

Grzegorz K. Karch

 

Other publications of authors with the same name

A Secure User Interface for Web Applications Running Under an Untrusted Operating System., , and . CIT, page 865-870. IEEE Computer Society, (2010)Synthesis of System-on-a-chip for Testability., and . VLSI Design, page 149-156. IEEE Computer Society, (2001)Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory., , , and . CICC, page 239-242. IEEE, (2005): Reducing test application time in high-level test generation., , and . ITC, page 829-838. IEEE Computer Society, (2000)Graceful Degradation in Algorithm-Based Fault Tolerant Multiprocessor Systems., and . ISCAS, page 333-336. IEEE, (1994)Synthesis of Fault Tolerant Architectures for Molecular Dynamics., and . ISCAS, page 247-250. IEEE, (1994)TAO: regular expression-based register-transfer level testability analysis and optimization., , and . IEEE Trans. VLSI Syst., 9 (6): 824-832 (2001)Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems., , , and . IEEE Trans. VLSI Syst., 15 (3): 296-308 (2007)Generation of distributed logic-memory architectures through high-level synthesis., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 24 (11): 1694-1711 (2005)Application-specific heterogeneous multiprocessor synthesis using extensible processors., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (9): 1589-1602 (2006)