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A holistic approach for tightly coupled reconfigurable parallel processors., , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 33 (1): 53-62 (2009)An Architecture Description Language for Massively Parallel Processor Architectures., , , , , and . MBMV, page 11-20. Fraunhofer Institut für Integrierte Schaltungen, (2006)Symbolic inner loop parallelisation for massively parallel processor arrays., , , and . MEMOCODE, page 219-228. IEEE, (2014)Acceleration of Multiresolution Imaging Algorithms: A Comparative Study., , , , and . ASAP, page 211-214. IEEE Computer Society, (2009)A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing., , , , and . ASAP, page 331-340. IEEE Computer Society, (2006)Domain-specific augmentations for High-Level Synthesis., , , , , and . ASAP, page 173-177. IEEE Computer Society, (2014)Mastering Software Variant Explosion for GPU Accelerators., , , , and . Euro-Par Workshops, volume 7640 of Lecture Notes in Computer Science, page 123-132. Springer, (2012)SYCL Code Generation for Multigrid Methods., , , and . SCOPES, page 41-44. ACM, (2019)Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays., , , and . ASAP, page 58-66. IEEE Computer Society, (2016)High-Speed Event-Driven RTL Compiled Simulation., , and . SAMOS, volume 3133 of Lecture Notes in Computer Science, page 519-529. Springer, (2004)