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Acceleration of Multiresolution Imaging Algorithms: A Comparative Study.

, , , , and . ASAP, page 211-214. IEEE Computer Society, (2009)

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Massively Parallel Processor Architectures: A Co-design Approach., , , , , , , , and . ReCoSoC, page 61-68. Univ. Montpellier II, (2007)Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology., , and . IPDPS, IEEE Computer Society, (2004)Acceleration of Multiresolution Imaging Algorithms: A Comparative Study., , , , and . ASAP, page 211-214. IEEE Computer Society, (2009)A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing., , , , and . ASAP, page 331-340. IEEE Computer Society, (2006)A holistic approach for tightly coupled reconfigurable parallel processors., , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 33 (1): 53-62 (2009)Regular mapping for coarse-grained reconfigurable architectures., , and . ICASSP (5), page 57-60. IEEE, (2004)A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation., , , , , and . ERSA, page 14-24. CSREA Press, (2007)Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors., , , and . SAMOS, volume 5657 of Lecture Notes in Computer Science, page 277-288. Springer, (2009)Synthesis and exploration of loop accelerators for systems-on-a-chip.. University of Erlangen-Nuremberg, (2011)Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis., , and . ARCS, volume 5455 of Lecture Notes in Computer Science, page 233-245. Springer, (2009)