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A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing.

, , , , and . ASAP, page 331-340. IEEE Computer Society, (2006)

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Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays., , and . J. Low Power Electronics, 7 (1): 29-40 (2011)Online placement for dynamically reconfigurable devices., , and . IJES, 1 (3/4): 165-178 (2005)Symbolic Quasi-Static Scheduling of Actor-Oriented SystemC Models., , and . FDL, page 1-6. IEEE, (2008)Parametric yield optimization using leakage-yield-driven floorplanning., , and . PATMOS, page 1-6. IEEE, (2014)A feasibility-preserving local search operator for constrained discrete optimization problems., , , and . IEEE Congress on Evolutionary Computation, page 1968-1975. IEEE, (2008)A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template., , , and . ReCoSoC, page 31-37. Univ. Montpellier II, (2006)Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators., , and . FCCM, page 279-282. IEEE Computer Society, (2009)Reconfigurable Computing Systems (Rekonfigurierbare Rechensysteme).. it - Information Technology, 49 (3): 139- (2007)Invasive Algorithms and Architectures (Invasive Algorithmen und Architekturen).. it - Information Technology, 50 (5): 300-310 (2008)Digitale Hardware/Software-Systeme - Synthese und Optimierung.. Springer, (1997)