%0 Journal Article %1 journals/jolpe/KisslerHT11 %A Kissler, Dmitrij %A Hannig, Frank %A Teich, Jürgen %D 2011 %J J. Low Power Electronics %K dblp %N 1 %P 29-40 %T Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays. %U http://dblp.uni-trier.de/db/journals/jolpe/jolpe7.html#KisslerHT11 %V 7

@article{journals/jolpe/KisslerHT11, added-at = {2011-05-12T00:00:00.000+0200}, author = {Kissler, Dmitrij and Hannig, Frank and Teich, Jürgen}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2a2768b589ddc8a5f2b4369c192bb7c04/dblp}, ee = {http://dx.doi.org/10.1166/jolpe.2011.1114}, interhash = {984e6957b57488b3cdc69e94c71bd697}, intrahash = {a2768b589ddc8a5f2b4369c192bb7c04}, journal = {J. Low Power Electronics}, keywords = {dblp}, number = 1, pages = {29-40}, timestamp = {2016-02-02T01:37:27.000+0100}, title = {Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays.}, url = {http://dblp.uni-trier.de/db/journals/jolpe/jolpe7.html#KisslerHT11}, volume = 7, year = 2011 }