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Coarse-grained reconfiguration.

S. Eisenhardt, T. Schweizer, J. de Oliveira Filho, T. Oppold, W. Rosenstiel, A. Thomas, J. Becker, F. Hannig, D. Kissler, H. Dutta, J. Teich, H. Hinkelmann, P. Zipf, and M. Glesner. FPL, page 349. IEEE, (2008)

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Modeling of Interconnection Networks in Massively Parallel Processor Architectures.A. Kupriyanov, F. Hannig, D. Kissler, J. Teich, J. Lallet, O. Sentieys, and S. Pillement. ARCS, volume 4415 of Lecture Notes in Computer Science, page 268-282. Springer, (2007)Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures.D. Kissler, A. Strawetz, F. Hannig, and J. Teich. J. Low Power Electronics, 5 (1): 96-105 (2009)A Generic Framework for Rapid Prototyping of System-on-Chip Designs.D. Kissler, A. Kupriyanov, F. Hannig, D. Koch, and J. Teich. CDES, page 189-195. CSREA Press, (2006)Coarse-grained reconfiguration.S. Eisenhardt, T. Schweizer, J. de Oliveira Filho, T. Oppold, W. Rosenstiel, A. Thomas, J. Becker, F. Hannig, D. Kissler, H. Dutta and 4 other author(s). FPL, page 349. IEEE, (2008)Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays.D. Kissler, F. Hannig, and J. Teich. J. Low Power Electronics, 7 (1): 29-40 (2011)A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template.D. Kissler, F. Hannig, A. Kupriyanov, and J. Teich. ReCoSoC, page 31-37. Univ. Montpellier II, (2006)A holistic approach for tightly coupled reconfigurable parallel processors.H. Dutta, D. Kissler, F. Hannig, A. Kupriyanov, J. Teich, and B. Pottier. Microprocessors and Microsystems - Embedded Hardware Design, 33 (1): 53-62 (2009)An Architecture Description Language for Massively Parallel Processor Architectures.A. Kupriyanov, F. Hannig, D. Kissler, J. Teich, R. Schaffer, and R. Merker. MBMV, page 11-20. Fraunhofer Institut für Integrierte Schaltungen, (2006)A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation.J. Teich, F. Hannig, H. Ruckdeschel, H. Dutta, D. Kissler, and A. Stravet. ERSA, page 14-24. CSREA Press, (2007)Efficient event-driven simulation of parallel processor architectures.A. Kupriyanov, D. Kissler, F. Hannig, and J. Teich. SCOPES, volume 235 of ACM International Conference Proceeding Series, page 71-80. (2007)

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Coarse-grained reconfiguration.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Coarse-grained reconfiguration.

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Coarse-grained reconfiguration.