Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Robust Brain-Inspired Computing : On the Reliability of Spiking Neural Network Using Emerging Non-Volatile Synapses

M. Wei, H. Amrouch, C. Sung, H. Lue, C. Yang, K. Wang, and C. Lu. 2021 IEEE International Reliability Physics Symposium (IRPS), Piscataway, IEEE, (2021)
DOI: 10.1109/IRPS46558.2021.9405141

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Xiliu Yang University of Stuttgart

Yayi Lin University of Stuttgart

Yang Wang University of Stuttgart

Guangpu Yang University of Stuttgart

Hsiu-Yu Yang University of Stuttgart

Other publications of authors with the same name

Memory access aware power gating for MPSoCs.Y. Lin, C. Yang, J. Huang, and N. Chang. ASP-DAC, page 121-126. IEEE, (2012)Reconfigurable Platform for Content Science Research.C. Shih, C. Yang, M. Ku, T. Kuo, S. Chien, Y. Chang, and L. Chen. RTCSA, page 481-486. IEEE Computer Society, (2005)A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters.S. Wang, S. Yang, H. Chen, C. Yang, and J. Wu. Signal Processing Systems, 57 (2): 195-211 (2009)Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs.C. Lin, S. Chen, C. Li, Y. Chang, and C. Yang. IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (4): 643-653 (2008)Memory Latency Reduction via Thread Throttling.H. Cheng, C. Lin, J. Li, and C. Yang. MICRO, page 53-64. IEEE Computer Society, (2010)Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation.P. Yuh, C. Yang, and Y. Chang. JETC, 3 (3): 13 (2007)System-Level Performance and Power Optimization for MPSoC: A Memory Access-Aware Approach.Y. Lin, C. Yang, J. Huang, T. Lin, C. Hsueh, and N. Chang. ACM Trans. Embedded Comput. Syst., 14 (1): 8:1-8:26 (2015)Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs.Y. Chen, C. Yang, P. Lin, and Y. Lu. RACS, page 430-436. ACM, (2015)Thermal modeling for 3D-ICs with integrated microchannel cooling.H. Mizunuma, C. Yang, and Y. Lu. ICCAD, page 256-263. ACM, (2009)Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture.P. Wang, C. Li, and C. Yang. DAC, page 5:1-5:6. ACM, (2016)