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Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs.

, , , and . RACS, page 430-436. ACM, (2015)

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A New Modulo (2n+1) Multiplier for IDEA., , and . Security and Management, page 318-324. CSREA Press, (2004)Thermal-aware task and data co-allocation for multi-processor system-on-chips with 3D-stacked memories., , and . RACS, page 243-248. ACM, (2018)Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs., , , and . RACS, page 430-436. ACM, (2015)Cache leakage control mechanism for hard real-time systems., , , and . CASES, page 248-256. ACM, (2007)Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMs., , , and . DATE, page 1-6. European Design and Automation Association, (2014)SECRET: Selective error correction for refresh energy reduction in DRAMs., , , , and . ICCD, page 67-74. IEEE Computer Society, (2012)TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems., , , and . IEEE Trans. Computers, 60 (6): 767-782 (2011)Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs., , and . ICCAD, page 458-465. ACM, (2012)PM-COSYN: PE and memory co-synthesis for MPSoCs., , and . DATE, page 1590-1595. IEEE, (2010)SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs., , , , and . TACO, 12 (2): 19:19:1-19:19:24 (2015)