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Disambiguation of "Wang, Po-Han"

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PM-COSYN: PE and memory co-synthesis for MPSoCs.

, , and . DATE, page 1590-1595. IEEE, (2010)

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Dr. Dongren Wang University of Stuttgart

Replication data of Buchmeiser group for: "Synthetic and Structural Peculiarities of Neutral and Cationic Molybdenum Imido and Tungsten Oxo Alkylidene Complexes Bearing Weakly Coordinating N-Heterocyclic Carbenes", , , , , , and . Dataset, (2024)Related to: M. R. Buchmeiser, D. Wang, R. Schowner, L. Stöhr, F. Ziegler, S. Sen, W. Frey,; Synthetic and Structural Peculiarities of Neutral and Cationic Molybdenum Imido and Tungsten Oxo Alkylidene Complexes Bearing Weakly Coordinating N-Heterocyclic Carbenes; Eur. J. Inorg. Chem., in press (2024). doi: 10.1002/ejic.202400082.

Liao Han University of Stuttgart

Qi Han

Univ. -Prof. Dr. Po Wen Cheng University of Stuttgart

Modeling, testing and application of tuned liquid multi-column dampers for floating offshore wind turbines. Universität Stuttgart, Stuttgart, Dissertation, (2024)

Zhe Wang University of Stuttgart

 

Other publications of authors with the same name

PM-COSYN: PE and memory co-synthesis for MPSoCs., , and . DATE, page 1590-1595. IEEE, (2010)Power gating strategies on GPUs., , , and . TACO, 8 (3): 13:1-13:25 (2011)Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator., , , , , , , , , and 9 other author(s). ISPASS, page 127-128. IEEE Computer Society, (2017)Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures., , and . DAC, page 112:1-112:6. ACM, (2018)Full system simulation framework for integrated CPU/GPU architecture., , , , , , , and . VLSI-DAT, page 1-4. IEEE, (2014)A Predictive Shutdown Technique for GPU Shader Processors., , , and . IEEE Comput. Archit. Lett., 8 (1): 9-12 (2009)A cycle-level SIMT-GPU simulation framework., , , and . ISPASS, page 114-115. IEEE Computer Society, (2012)Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling., , , and . IEEE Comput. Archit. Lett., 16 (2): 127-131 (2017)Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture., , and . DAC, page 5:1-5:6. ACM, (2016)A 0.6V 75nW All-CMOS Temperature Sensor With 1.67m°C/mV Supply Sensitivity., , , and . IEEE Trans. on Circuits and Systems, 64-I (9): 2274-2283 (2017)