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Full system simulation framework for integrated CPU/GPU architecture.

P. Wang, G. Liu, J. Yeh, T. Chen, H. Huang, C. Yang, S. Liu, and J. Greensky. VLSI-DAT, page 1-4. IEEE, (2014)

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Jen Sikos

Sabrina Jenne University of Stuttgart

Marcus Jenke

Christopher Jenkins University of Stuttgart

Marcus Jenke

Other publications of authors with the same name

System power analysis with DVFS on ESL virtual platform.W. Hsieh, J. Yeh, S. Lin, H. Liu, and Y. Chen. SoCC, page 93-98. IEEE, (2011)Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs.S. Chen, C. Hsu, H. Shih, J. Yeh, and C. Wu. ASP-DAC, page 429-434. IEEE, (2013)An accurate system architecture refinement methodology with mixed abstraction-level virtual platform.Z. Hsu, J. Yeh, and I. Chuang. DATE, page 568-573. IEEE, (2010)A Cycle Count Accurate TLM bus modeling approach.M. Li, C. Lo, L. Chen, J. Yeh, and R. Tsay. VLSI-DAT, page 1-4. IEEE, (2013)A Systematic Approach to Memory Test Time Reduction.J. Yeh, C. Chen, C. Wu, and S. Kuo. IEEE Design & Test of Computers, 25 (6): 560-570 (2008)A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories.R. Huang, J. Li, J. Yeh, and C. Wu. MTDT, page 68-. IEEE Computer Society, (2002)Flash Memory Die Sort by a Sample Classification Method.Y. Dawn, J. Yeh, C. Wu, C. Wang, Y. Lin, and C. Chen. Asian Test Symposium, page 182-187. IEEE Computer Society, (2005)Diagonal Test and Diagnostic Schemes for Flash Memorie.S. Chiu, J. Yeh, C. Huang, and C. Wu. ITC, page 37-46. IEEE Computer Society, (2002)System Performance Analyses on PAC Duo ESL Virtual Platform.Z. Hsu, I. Chuang, W. Su, J. Yeh, J. Yang, and S. Tseng. IIH-MSP, page 406-409. IEEE Computer Society, (2009)Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus.C. Lo, M. Li, L. Chen, Y. Lu, R. Tsay, H. Huang, and J. Yeh. ACM Trans. Embedded Comput. Syst., 13 (1s): 37:1-37:25 (2013)

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Disambiguation of "Yeh, Jen-Chieh"

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Full system simulation framework for integrated CPU/GPU architecture.

Please choose a person to relate this publication to

Jen Sikos

Sabrina Jenne University of Stuttgart

Marcus Jenke

Christopher Jenkins University of Stuttgart

Marcus Jenke

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Yeh, Jen-Chieh"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Full system simulation framework for integrated CPU/GPU architecture.

Please choose a person to relate this publication to

Jen Sikos

Sabrina Jenne University of Stuttgart

Marcus Jenke

Christopher Jenkins University of Stuttgart

Marcus Jenke

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Full system simulation framework for integrated CPU/GPU architecture.