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Diagonal Test and Diagnostic Schemes for Flash Memorie.

, , , and . ITC, page 37-46. IEEE Computer Society, (2002)

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Application-specific CAD of VLSI second-order sections., and . IEEE Trans. Acoustics, Speech, and Signal Processing, 36 (5): 813-825 (1988)An Application-Independent Delay Testing Methodology for Island-Style FPGA., , , and . DFT, page 478-486. IEEE Computer Society, (2004)Test Energy Minimization for C-Testable ILAs., and . J. Inf. Sci. Eng., 15 (6): 899-911 (1999)Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults., , , , , and . J. Inf. Sci. Eng., 19 (4): 571-587 (2003)Relating Tiling and Coloring to Testing of Combinational Iterative Logic Arrays.. J. Inf. Sci. Eng., 6 (1): 63-72 (1990)Does There Exist a Combinational TSC Checker for 1/3 Code Using Only Primitive Gates?, and . J. Inf. Sci. Eng., 13 (4): 681-695 (1997)SOC Test Architecture and Method for 3-D ICs., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (10): 1645-1649 (2010)An Adaptive-Rate Error Correction Scheme for NAND Flash Memory., , , and . VTS, page 53-58. IEEE Computer Society, (2009)Test and Diagnosis of Word-Oriented Multiport Memories., , , and . VTS, page 248-253. IEEE Computer Society, (2003)Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories., , and . VTS, page 225-230. IEEE Computer Society, (2001)