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Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation.

, , and . JETC, 3 (3): 13 (2007)

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Timing-driven routing for symmetrical-array-based FPGAs., , and . ICCD, page 628-633. (1998)Global Interconnect Planning., , and . Handbook of Algorithms for Physical Design Automation, Auerbach Publications, (2008)Multilayer Global Routing With Via and Wire Capacity Considerations., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (5): 685-696 (2010)ECO Optimization Using Metal-Configurable Gate-Array Spare Cells., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (11): 1722-1733 (2013)Escape Routing for Staggered-Pin-Array PCBs., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (9): 1347-1356 (2013)Pulsed-Latch Aware Placement for Timing-Integrity Optimization., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (12): 1856-1869 (2011)Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (6): 1041-1053 (2007)Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (11): 1649-1662 (2011)Analog Placement Based on Symmetry-Island Formulation., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 28 (6): 791-804 (2009)TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (4): 497-509 (2013)