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Multilayer Global Routing With Via and Wire Capacity Considerations.

, , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (5): 685-696 (2010)

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Multilayer Global Routing With Via and Wire Capacity Considerations., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (5): 685-696 (2010)GasStation: Power and Area Efficient Buffering for Multiple Power Domain Design., , and . ICCAD, page 861-866. IEEE, (2015)A new measuring fixator design for humeral supracondylar corrective osteotomies in children., , , , and . SMC, page 2915-2919. IEEE, (2003)An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 28 (1): 98-110 (2009)High-performance global routing with fast overflow reduction., , and . ASP-DAC, page 582-587. IEEE, (2009)Multi-layer global routing considering via and wire capacities., , and . ICCAD, page 350-355. IEEE Computer Society, (2008)An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design., , and . DAC, page 606-611. IEEE, (2007)Simultaneous Layout Migration and Decomposition for Double Patterning Technology., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (2): 284-294 (2011)A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits., , , and . PATMOS, volume 4644 of Lecture Notes in Computer Science, page 148-159. Springer, (2007)Simultaneous layout migration and decomposition for double patterning technology., , and . ICCAD, page 595-600. ACM, (2009)