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Disambiguation of "Shin, Youngsoo"

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Pulsed-Latch Aware Placement for Timing-Integrity Optimization.

, , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (12): 1856-1869 (2011)

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Ji Eun Shin University of Stuttgart

Abhishekkumar Shingala University of Stuttgart

 

Other publications of authors with the same name

Introducing irregularity to routing architecture of structured ASIC for better routability., , and . FPT, page 224-228. IEEE, (2012)Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits., , , and . IEEE Trans. VLSI Syst., 15 (7): 758-766 (2007)Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation., , and . IEEE Trans. on Circuits and Systems, 62-I (2): 468-477 (2015)Semicustom Design Methodology of Power Gated Circuits for Low Leakage Applications., and . IEEE Trans. on Circuits and Systems, 54-II (6): 512-516 (2007)Prosocial Activists in SNS: The Impact of Isomorphism and Social Presence on Prosocial Behaviors., , and . Int. J. Hum. Comput. Interaction, 31 (12): 939-958 (2015)Narrow bus encoding for low-power DSP systems., , and . IEEE Trans. VLSI Syst., 9 (5): 656-660 (2001)Pulsed-Latch Aware Placement for Timing-Integrity Optimization., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (12): 1856-1869 (2011)Clock Gating Synthesis of Pulsed-Latch Circuits., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (7): 1019-1030 (2012)Identifying redundant inter-cell margins and its application to reducing routing congestion., , and . DATE, page 1659-1664. ACM, (2015)Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power., , and . ICCAD, page 640-646. IEEE Computer Society, (2011)