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Disambiguation of "Cheng, Hsiang-Yun"

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Memory Latency Reduction via Thread Throttling.

, , , and . MICRO, page 53-64. IEEE Computer Society, (2010)

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Xiaoyu Cheng University of Stuttgart

Tiffany Cheng University of Stuttgart

Univ. -Prof. Dr. Po Wen Cheng University of Stuttgart

Yingxing Cheng University of Stuttgart

Cheng-I Ho University of Stuttgart

 

Other publications of authors with the same name

Memory Latency Reduction via Thread Throttling., , , and . MICRO, page 53-64. IEEE Computer Society, (2010)LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches., , , , , , and . ISCA, page 103-114. IEEE Computer Society, (2016)EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors., , , , , , , and . ISLPED, page 303-306. ACM, (2014)Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling., , , and . IEEE Comput. Archit. Lett., 16 (2): 127-131 (2017)Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference., , and . ACM Trans. Design Autom. Electr. Syst., 21 (1): 7:1-7:26 (2015)EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors., , , , , , , and . TACO, 12 (2): 17:1-17:22 (2015)Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks., , , , , , and . ISCA, page 236-249. ACM, (2019)LIRS: Enabling efficient machine learning on NVM-based storage via a lightweight implementation of random shuffling., , and . CoRR, (2018)DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning., , , , , , , , , and . ICCAD, page 31. ACM, (2018)Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator., , , , , , , , , and 9 other author(s). ISPASS, page 127-128. IEEE Computer Society, (2017)