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Belief Revision and Dynamic Logic.

, and . Johan van Benthem on Logic and Information Dynamics, Springer, (2014)

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Everything Else Being Equal: A Modal Logic for Ceteris Paribus Preferences., , and . J. Philosophical Logic, 38 (1): 83-125 (2009)Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives., , , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 540-549. Springer, (2005)Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity., , , , , , , and . ISCAS (1), page 110-113. IEEE, (1999)Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution., , , , , and . Asian Test Symposium, page 266-271. IEEE Computer Society, (2004)A Mixed Approach for Unified Logic Diagnosis., , , , , and . DDECS, page 239-242. IEEE Computer Society, (2007)SoC Symbolic Simulation: a case study on delay fault testing., , , and . DDECS, page 320-325. IEEE Computer Society, (2008)Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture., , , , and . IOLTS, page 89-94. IEEE, (2015)Delay Fault Diagnosis in Sequential Circuits., , , , , , and . Asian Test Symposium, page 355-360. IEEE Computer Society, (2009)A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation., , , and . Great Lakes Symposium on VLSI, page 24-. IEEE Computer Society, (1999)Low Power Testing of VLSI Circuits: Problems and Solutions.. ISQED, page 173-180. IEEE Computer Society, (2000)