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Disambiguation of "Guiller, Loïs"

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A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation.

, , , and . Great Lakes Symposium on VLSI, page 24-. IEEE Computer Society, (1999)

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Other publications of authors with the same name

Power-Driven Routing-Constrained Scan Chain Design., , , , and . J. Electronic Testing, 20 (6): 647-660 (2004)Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption., , , and . Asian Test Symposium, page 89-94. IEEE Computer Society, (1999)Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity., , , , , , , and . ISCAS (1), page 110-113. IEEE, (1999)Low Power BIST by Filtering Non-Detecting Vectors., , , , , , , , , and . J. Electronic Testing, 16 (3): 193-202 (2000)A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores., , , , and . Asian Test Symposium, page 253-258. IEEE Computer Society, (2001)A Modified Clock Scheme for a Low Power BIST Test Pattern Generator., , , , and . VTS, page 306-311. IEEE Computer Society, (2001)Low Power BIST by Filtering Non-Detecting Vectors., , , , , , , , , and . J. Electronic Testing, 16 (3): 193-202 (2000)Integrating DFT in the Physical Synthesis Flow., , , , and . ITC, page 788-795. IEEE Computer Society, (2002)Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity., , , , , , , and . ISCAS (1), page 110-113. IEEE, (1999)A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation., , , and . Great Lakes Symposium on VLSI, page 24-. IEEE Computer Society, (1999)