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Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture.

I. Wali, A. Virazel, A. Bosio, P. Girard, and M. Reorda. IOLTS, page 89-94. IEEE, (2015)

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A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits.I. Wali, B. Deveautour, A. Virazel, A. Bosio, P. Girard, and M. Reorda. J. Electronic Testing, 33 (1): 25-36 (2017)A low-cost susceptibility analysis methodology to selectively harden logic circuits.I. Wali, B. Deveautour, A. Virazel, A. Bosio, P. Girard, and M. Reorda. ETS, page 1-2. IEEE, (2016)Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults.I. Wali, A. Virazel, A. Bosio, L. Dilillo, P. Girard, and A. Todri. DDECS, page 223-225. IEEE Computer Society, (2014)Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture.I. Wali, A. Virazel, A. Bosio, P. Girard, and M. Reorda. IOLTS, page 89-94. IEEE, (2015)An effective hybrid fault-tolerant architecture for pipelined cores.I. Wali, A. Virazel, A. Bosio, L. Dilillo, and P. Girard. ETS, page 1-6. IEEE, (2015)Towards approximation during test of Integrated Circuits.I. Wali, M. Traiola, A. Virazel, P. Girard, M. Barbareschi, and A. Bosio. DDECS, page 28-33. IEEE, (2017)A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores.I. Wali, A. Virazel, A. Bosio, P. Girard, S. Pravossoudovitch, and M. Reorda. J. Electronic Testing, 32 (2): 147-161 (2016)

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Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture.

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Disambiguation of "Wali, Imran"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture.

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Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture.