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Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults.

I. Wali, A. Virazel, A. Bosio, L. Dilillo, P. Girard, and A. Todri. DDECS, page 223-225. IEEE Computer Society, (2014)

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Patrick Maisenhölder University of Stuttgart

Patrick Lerge University of Stuttgart

Patrick Hippold University of Stuttgart

Patrick Gralka University of Stuttgart

Patrick Fleischmann University of Stuttgart

Other publications of authors with the same name

An effective hybrid fault-tolerant architecture for pipelined cores.I. Wali, A. Virazel, A. Bosio, L. Dilillo, and P. Girard. ETS, page 1-6. IEEE, (2015)Belief Revision and Dynamic Logic.P. Girard, and H. Rott. Johan van Benthem on Logic and Information Dynamics, Springer, (2014)Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch. ITC, page 488-493. IEEE Computer Society, (2003)Power Driven Chaining of Flip-Flops in Scan Architectures.Y. Bonhomme, P. Girard, C. Landrault, and S. Pravossoudovitch. ITC, page 796-803. IEEE Computer Society, (2002)Logical dynamics of belief change in the community.F. Liu, J. Seligman, and P. Girard. Synthese, 191 (11): 2403-2431 (2014)Vérification de cohérence entre modèles de tâches et de dialogue en conception centrée-utilisateur.S. Caffiau, P. Girard, L. Guittet, and X. Blanc. Ingénierie des Systèmes d'Information, 16 (5): 9-41 (2011)Delay-Fault Diagnosis by Critical-Path Tracing.P. Girard, C. Landrault, and S. Pravossoudovitch. IEEE Design & Test of Computers, 9 (4): 27-32 (1992)A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk.J. Ma, M. Tehranipoor, and P. Girard. J. Electronic Testing, 28 (2): 201-214 (2012)Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories.L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, S. Borri, and M. Hage-Hassan. J. Electronic Testing, 21 (5): 551-561 (2005)A Ring Architecture Strategy for BIST Test Pattern Generation.C. Fagot, O. Gascuel, P. Girard, and C. Landrault. J. Electronic Testing, 19 (3): 223-231 (2003)

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Disambiguation of "Girard, Patrick"

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Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults.

Please choose a person to relate this publication to

Patrick Maisenhölder University of Stuttgart

Patrick Lerge University of Stuttgart

Patrick Hippold University of Stuttgart

Patrick Gralka University of Stuttgart

Patrick Fleischmann University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Girard, Patrick"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults.

Please choose a person to relate this publication to

Patrick Maisenhölder University of Stuttgart

Patrick Lerge University of Stuttgart

Patrick Hippold University of Stuttgart

Patrick Gralka University of Stuttgart

Patrick Fleischmann University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults.