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Disambiguation of "Chen, Hung-Ming"

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PAGE: parallel agile genetic exploration towards utmost performance for analog circuit design.

, , and . DATE, page 1849-1854. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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Hong Chen University of Stuttgart

Univ. -Prof. Klaus-Dieter Hungenberg University of Stuttgart

Katrin Hungerbühler University of Stuttgart

Yiyin Chen University of Stuttgart

Jun Chen University of Stuttgart

 

Other publications of authors with the same name

On Achieving Low-Power SoC Clock Tree Synthesis by Transition Time Planning via Buffer Library Study., and . SoCC, page 203-206. IEEE, (2006)Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design., , , and . SoCC, page 211-214. IEEE, (2006)Board- and Chip-Aware Package Wire Planning., , and . IEEE Trans. VLSI Syst., 21 (8): 1377-1387 (2013)Fast Flip-Chip Pin-Out Designation Respin for Package-Board Codesign., and . IEEE Trans. VLSI Syst., 17 (8): 1087-1098 (2009)Striking the Balance between Content Diversity and Content Importance in Swarm-Based P2P Streaming System., , and . HPCC, page 653-660. IEEE, (2011)Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits., , and . J. Inf. Sci. Eng., 27 (1): 287-302 (2011)PAGE: parallel agile genetic exploration towards utmost performance for analog circuit design., , and . DATE, page 1849-1854. EDA Consortium San Jose, CA, USA / ACM DL, (2013)A network-flow based algorithm for power density mitigation at post-placement stage., , and . DATE, page 1707-1710. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Cost-effective decap selection for beyond die power integrity., , , and . DATE, page 1-4. European Design and Automation Association, (2014)Mixed non-rectangular block packing for non-Manhattan layout architectures., , and . ISQED, page 257-262. IEEE, (2011)