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Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design.

, , , and . SoCC, page 211-214. IEEE, (2006)

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Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits., , and . J. Inf. Sci. Eng., 27 (1): 287-302 (2011)New Sorting Technique on Partial Distortion Search Using Two Bit-Transform for Fast Optimal Motion Estimation., , and . RVSP, page 276-279. IEEE Computer Society, (2011)Joint Cluster Routing and Sleep-Awake Scheduling for Energy-Efficiency in Wireless Sensor Networks., , , , and . iThings/GreenCom/CPSCom, page 526-531. IEEE Computer Society, (2014)Routability-driven bump assignment for chip-package co-design., , , and . ASP-DAC, page 519-524. IEEE, (2014)Text Classification Using Web Corpora and EM Algorithms., and . AIRS, volume 3411 of Lecture Notes in Computer Science, page 12-23. Springer, (2004)Multi-level droplet routing in active-matrix based digital-microfluidic biochips., , , and . ASP-DAC, page 46-51. IEEE, (2018)Faster and more accurate wiring evaluation in interconnect-centric floorplanning., , , and . ACM Great Lakes Symposium on VLSI, page 62-67. ACM, (2001)Fast analog layout prototyping for nanometer design migration., , , , , and . ICCAD, page 517-522. IEEE Computer Society, (2011)尋易(Csmart-Ⅱ):智慧型網路中文資訊檢索系統 (An Intelligent Chinese Information Retrieval System for the Internet) In Chinese., , , , , , , , and . ROCLING, page 121-136. The Association for Computational Linguistics and Chinese Language Processing (ACLCLP), (1996)Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations., and . ISPD, page 23-30. ACM, (2008)