%0 Journal Article %1 journals/jise/LuCL11 %A Lu, Chao-Hung %A Chen, Hung-Ming %A Liu, Chien-Nan Jimmy %D 2011 %J J. Inf. Sci. Eng. %K dblp %N 1 %P 287-302 %T Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits. %U http://dblp.uni-trier.de/db/journals/jise/jise27.html#LuCL11 %V 27

@article{journals/jise/LuCL11, added-at = {2011-01-26T00:00:00.000+0100}, author = {Lu, Chao-Hung and Chen, Hung-Ming and Liu, Chien-Nan Jimmy}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2945abff61f781868997bb34b27ff7fff/dblp}, ee = {http://www.iis.sinica.edu.tw/page/jise/2011/201101_18.html}, interhash = {7f48eea6191b03ed18b476d5d31195e3}, intrahash = {945abff61f781868997bb34b27ff7fff}, journal = {J. Inf. Sci. Eng.}, keywords = {dblp}, number = 1, pages = {287-302}, timestamp = {2016-02-02T10:21:01.000+0100}, title = {Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits.}, url = {http://dblp.uni-trier.de/db/journals/jise/jise27.html#LuCL11}, volume = 27, year = 2011 }