%0 Conference Paper %1 conf/socc/LuWCJ06 %A Lu, Ming-Ching %A Wu, Meng-Chen %A Chen, Hung-Ming %A Jiang, Iris Hui-Ru %B SoCC %D 2006 %I IEEE %K dblp %P 211-214 %T Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design. %U http://dblp.uni-trier.de/db/conf/socc/socc2006.html#LuWCJ06 %@ 0-7803-9781-9

@inproceedings{conf/socc/LuWCJ06, added-at = {2012-06-05T00:00:00.000+0200}, author = {Lu, Ming-Ching and Wu, Meng-Chen and Chen, Hung-Ming and Jiang, Iris Hui-Ru}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/298135c66ba606f5a6c1b78bc9077d8dd/dblp}, booktitle = {SoCC}, crossref = {conf/socc/2006}, ee = {http://dx.doi.org/10.1109/SOCC.2006.283883}, interhash = {961e5c5cb792fcde1c9752f53d88bcfe}, intrahash = {98135c66ba606f5a6c1b78bc9077d8dd}, isbn = {0-7803-9781-9}, keywords = {dblp}, pages = {211-214}, publisher = {IEEE}, timestamp = {2016-02-02T11:49:44.000+0100}, title = {Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design.}, url = {http://dblp.uni-trier.de/db/conf/socc/socc2006.html#LuWCJ06}, year = 2006 }