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Disambiguation of "Keller, Ben"

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A Pausible Bisynchronous FIFO for GALS Systems.

, , and . ASYNC, page 1-8. IEEE Computer Society, (2015)

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Jonas Keller University of Stuttgart

Achim Benz University of Stuttgart

Alexander Keller

Alexander Keller

Prof. Dr. Paul Keller University of Stuttgart

 

Other publications of authors with the same name

An Agile Approach to Building RISC-V Microprocessors., , , , , , , , , and 8 other author(s). IEEE Micro, 36 (2): 8-20 (2016)A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI., , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)Reply to discussion by B. Keller and R. Nance., and . Journal of Software Maintenance, 7 (5): 379-380 (1995)A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI., , , , , , , , , and 4 other author(s). J. Solid-State Circuits, 52 (7): 1863-1875 (2017)A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI., , , , , , , , , and 9 other author(s). VLSIC, page 316-. IEEE, (2015)PRIMAL: Power Inference using Machine Learning., , , , , and . DAC, page 39. ACM, (2019)Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC., , , , , , , , , and 4 other author(s). ESSCIRC, page 269-272. IEEE, (2016)A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm., , , , , , , , , and 7 other author(s). VLSI Circuits, page 300-. IEEE, (2019)A Pausible Bisynchronous FIFO for GALS Systems., , and . ASYNC, page 1-8. IEEE Computer Society, (2015)A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 55 (4): 920-932 (2020)