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Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories., , , , , and . J. Electronic Testing, 21 (5): 551-561 (2005)Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution., , , , , and . Asian Test Symposium, page 266-271. IEEE Computer Society, (2004)Delay Fault Diagnosis in Sequential Circuits., , , , , , and . Asian Test Symposium, page 355-360. IEEE Computer Society, (2009)A built-in scheme for testing and repairing voltage regulators of low-power srams., , , , , , and . VTS, page 1-6. IEEE Computer Society, (2013)Effect-cause intra-cell diagnosis at transistor level., , , , , , and . ISQED, page 460-467. IEEE, (2013)An effective hybrid fault-tolerant architecture for pipelined cores., , , , and . ETS, page 1-6. IEEE, (2015)A study of path delay variations in the presence of uncorrelated power and ground supply noise., , , , , and . DDECS, page 189-194. IEEE Computer Society, (2011)On using a SPICE-like TSTAC™ eFlash model for design and test., , , , , , , , and . DDECS, page 359-364. IEEE Computer Society, (2011)Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling., , , , , , and . DDECS, page 353-358. IEEE Computer Society, (2011)An effective ATPG flow for Gate Delay Faults., , , , , and . DTIS, page 1-6. IEEE, (2015)