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A built-in scheme for testing and repairing voltage regulators of low-power srams.

, , , , , , and . VTS, page 1-6. IEEE Computer Society, (2013)

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Improving SRAM test quality by leveraging self-timed circuits, , , and . 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), page 984-989. Piscataway, IEEE, (2016)On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs., , , , , , and . ITC, page 1-10. IEEE Computer Society, (2013)On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs, , and . 2015 IEEE 24th Asian Test Symposium (ATS), page 61-66. Piscataway, IEEE, (2015)An effective BIST architecture for power-gating mechanisms in low-power SRAMs., , , , and . ISQED, page 185-191. IEEE, (2016)Test solution for data retention faults in low-power SRAMs., , , , , , and . DATE, page 442-447. EDA Consortium San Jose, CA, USA / ACM DL, (2013)On the Test and Mitigation of Malfunctions in Low-Power SRAMs., , , , , and . J. Electronic Testing, 30 (5): 611-627 (2014)A built-in scheme for testing and repairing voltage regulators of low-power srams., , , , , , and . VTS, page 1-6. IEEE Computer Society, (2013)Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling., , , , , , and . DDECS, page 353-358. IEEE Computer Society, (2011)Failure Analysis and Test Solutions for Low-Power SRAMs., , , , , , , and . Asian Test Symposium, page 459-460. IEEE Computer Society, (2011)Defect analysis in power mode control logic of low-power SRAMs., , , , , , and . European Test Symposium, page 1. IEEE Computer Society, (2012)