Author of the publication

Analysis of triggering behaviour of high voltage CMOS LDMOS clamps and SCRs during ESD induced latch-up.

, , , , , , , and . Microelectronics Reliability, 46 (9-11): 1591-1596 (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Transient interferometric mapping of carrier plasma during external transient latch-up phenomena in latch-up test structures and I/O cells processed in CMOS technology., , , , , , and . Microelectronics Reliability, 49 (12): 1455-1464 (2009)Scanning heterodyne interferometer setup for the time-resolved thermal and free-carrier mapping in semiconductor devices., , , , and . IEEE Trans. Instrumentation and Measurement, 54 (6): 2438-2445 (2005)Study of internal behavior in a vertical DMOS transistor under short high current stress by an interferometric mapping method., , , , , and . Microelectronics Reliability, 43 (4): 545-548 (2003)Multiple-time-instant 2D thermal mapping during a single ESD event., , , , , , , , , and . Microelectronics Reliability, 44 (9-11): 1793-1798 (2004)Electrical field mapping in InGaP HEMTs and GaAs terahertz emitters using backside infrared OBIC technique., , , , , , , , , and . Microelectronics Reliability, 42 (9-11): 1673-1677 (2002)Thermal and free carrier laser interferometric mapping and failure analysis of anti-serial smart power ESD protection structures., , , , , , and . Microelectronics Reliability, 41 (9-10): 1501-1506 (2001)Transient interferometric mapping of smart power SOI ESD protection devices under TLP and vf-TLP stress., , , , , , and . Microelectronics Reliability, 44 (9-11): 1687-1692 (2004)Automated setup for thermal imaging and electrical degradation study of power DMOS devices., , , , , , , , and . Microelectronics Reliability, 45 (9-11): 1688-1693 (2005)Application of transient interferometric mapping method for ESD and latch-up analysis., , , , and . Microelectronics Reliability, 51 (9-11): 1592-1596 (2011)Thermal imaging of smart power DMOS transistors in the thermally unstable regime using a compact transient interferometric mapping system., , , , , , , , and . Microelectronics Reliability, 49 (9-11): 1346-1351 (2009)