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Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation.

, , , , and . VLSI Design, page 382-387. IEEE Computer Society, (2012)

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ATPG-based grading of strong fault-secureness., , , , and . IOLTS, page 269-274. IEEE Computer Society, (2009)Evolutionary Optimization in Code-Based Test Compression, , and . CoRR, (2007)TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis., , , , , and . VLSI Design, page 227-232. IEEE Computer Society, (2009)Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation., , , , and . VLSI Design, page 382-387. IEEE Computer Society, (2012)Estimation of component criticality in early design steps., , , and . IOLTS, page 104-110. IEEE Computer Society, (2011)Evolutionary Optimization in Code-Based Test Compression., , and . DATE, page 1124-1129. IEEE Computer Society, (2005)Dynamic Compaction in SAT-Based ATPG., , , , and . Asian Test Symposium, page 187-190. IEEE Computer Society, (2009)Power Droop Testing., , , and . ICCD, page 243-250. IEEE, (2006)An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects., , , , , , and . VTS, page 21-26. IEEE Computer Society, (2009)Efficient SAT-Based Search for Longest Sensitisable Paths., , , , and . Asian Test Symposium, page 108-113. IEEE Computer Society, (2011)