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Disambiguation of "Polian, Ilia"

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Evolutionary Optimization in Code-Based Test Compression.

, , and . DATE, page 1124-1129. IEEE Computer Society, (2005)

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Univ. -Prof. Dr. rer. nat. Ilia Polian University of Stuttgart

 

Other publications of authors with the same name

Power Supply Noise: Causes, Effects, and Testing.. J. Low Power Electronics, 6 (2): 326-338 (2010)Nichtstandardfehlermodelle für digitale Logikschaltkreise: Simulation, prüfgerechter Entwurf, industrielle Anwendungen (On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications).. it - Information Technology, 47 (3): 172-174 (2005)Hardware security and test: Friends or enemies?. it - Information Technology, 56 (4): 192-202 (2014)Scalable Delay Fault BIST for Use with Low-Cost ATE., and . J. Electronic Testing, 20 (2): 181-197 (2004)On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (2): 327-338 (2008)Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays., , , , , , and . LATW, page 1-6. IEEE Computer Society, (2013)Protecting cryptographic hardware against malicious attacks by nonlinear robust codes., , , , and . DFT, page 40-45. IEEE Computer Society, (2014)Special session 4B: Panel low-power test and noise-aware test: Foes or friends?. VTS, page 130. IEEE Computer Society, (2010)A Family of Logical Fault Models for Reversible Circuits., , , and . Asian Test Symposium, page 422-427. IEEE Computer Society, (2005)Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths., , , , and . DATE, page 448-453. EDA Consortium San Jose, CA, USA / ACM DL, (2013)