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Efficient SAT-Based Search for Longest Sensitisable Paths.

, , , , and . Asian Test Symposium, page 108-113. IEEE Computer Society, (2011)

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Nichtstandardfehlermodelle für digitale Logikschaltkreise: Simulation, prüfgerechter Entwurf, industrielle Anwendungen (On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications).. it - Information Technology, 47 (3): 172-174 (2005)Hardware security and test: Friends or enemies?. it - Information Technology, 56 (4): 192-202 (2014)Fault-based attacks on cryptographic hardware., and . DDECS, page 12-17. IEEE Computer Society, (2013)Diagnosis of Realistic Defects Based on the X-Fault Model., , , , , , , and . DDECS, page 263-266. IEEE Computer Society, (2008)A Family of Logical Fault Models for Reversible Circuits., , , and . Asian Test Symposium, page 422-427. IEEE Computer Society, (2005)Protecting cryptographic hardware against malicious attacks by nonlinear robust codes., , , , and . DFT, page 40-45. IEEE Computer Society, (2014)Special session 4B: Panel low-power test and noise-aware test: Foes or friends?. VTS, page 130. IEEE Computer Society, (2010)Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths., , , , and . DATE, page 448-453. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Tomographic Testing and Validation of Probabilistic Circuits., , , and . European Test Symposium, page 63-68. IEEE Computer Society, (2011)Multi-Stage Fault Attacks on Block Ciphers., , and . IACR Cryptology ePrint Archive, (2013)