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Disambiguation of "Link, Greg M."

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Interconnect and Thermal-aware Floorplanning for 3D Microprocessors.

, , , , and . ISQED, page 98-104. IEEE Computer Society, (2006)

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Maike Link University of Stuttgart

Lukas Link University of Stuttgart

Patrick Linker University of Stuttgart

Cosimo Gregucci University of Stuttgart

M. Nudischer

 

Other publications of authors with the same name

Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip., , , and . Advances in Computers, (2005)Interconnect and Thermal-aware Floorplanning for 3D Microprocessors., , , , and . ISQED, page 98-104. IEEE Computer Society, (2006)A generic reconfigurable neural network architecture as a network on chip., , , , and . SoCC, page 191-194. IEEE, (2004)Load Miss Prediction - Exploiting Power Performance Trade-offs., , , and . IPDPS, page 1-8. IEEE, (2007)A Holistic Approach to Designing Energy-Efficient Cluster Interconnects., , , , , , and . IEEE Trans. Computers, 54 (6): 660-671 (2005)Implementing LDPC Decoding on Network-on-Chip., , , and . VLSI Design, page 134-137. IEEE Computer Society, (2005)Energy optimization techniques in cluster interconnects., , , , , , , and . ISLPED, page 459-464. ACM, (2003)Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers., , , , , , and . IEEE Trans. on Circuits and Systems, 56-I (2): 374-383 (2009)Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures., , , , and . Asia-Pacific Computer Systems Architecture Conference, volume 3740 of Lecture Notes in Computer Science, page 200-214. Springer, (2005)Thermally robust clocking schemes for 3D integrated circuits., , , , , , and . DATE, page 1206-1211. EDA Consortium, San Jose, CA, USA, (2007)