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Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip.

T. Theocharides, G. Link, N. Vijaykrishnan, and M. Irwin. Advances in Computers, (2005)

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Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications.K. Ma, X. Li, S. Li, Y. Liu, J. Sampson, Y. Xie, and V. Narayanan. IEEE Micro, 35 (5): 32-40 (2015)Tunnel FET RF Rectifier Design for Energy Harvesting Applications.H. Liu, X. Li, R. Vaddi, K. Ma, S. Datta, and V. Narayanan. IEEE J. Emerg. Sel. Topics Circuits Syst., 4 (4): 400-411 (2014)Energy-performance trade-offs for spatial access methods on memory-resident data.N. An, S. Gurumurthi, A. Sivasubramaniam, N. Vijaykrishnan, M. Kandemir, and M. Irwin. VLDB J., 11 (3): 179-197 (2002)Managing Leakage Energy in Cache Hierarchies.L. Li, I. Kadayif, Y. Tsai, N. Vijaykrishnan, M. Kandemir, M. Irwin, and A. Sivasubramaniam. J. Instruction-Level Parallelism, (2003)Java Runtime Systems: Characterization and Architectural Implications.R. Radhakrishnan, N. Vijaykrishnan, L. John, A. Sivasubramaniam, J. Rubio, and J. Sabarinathan. IEEE Trans. Computers, 50 (2): 131-146 (2001)Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues.A. Gayasen, N. Vijaykrishnan, M. Kandemir, and A. Rahman. IEEE Trans. VLSI Syst., 16 (7): 882-893 (2008)An integer linear programming-based tool for wireless sensor networks.I. Kadayif, M. Kandemir, N. Vijaykrishnan, and M. Irwin. J. Parallel Distrib. Comput., 65 (3): 247-260 (2005)Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers.T. Ragheb, A. Ricketts, M. Mondal, S. Kirolos, G. Link, V. Narayanan, and Y. Massoud. IEEE Trans. on Circuits and Systems, 56-I (2): 374-383 (2009)Network-on-Chip Architectures - A Holistic Design ExplorationC. Nicopoulos, V. Narayanan, and C. Das. Lecture Notes in Electrical Engineering Springer, (2010)Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks.D. Duarte, N. Vijaykrishnan, M. Irwin, and M. Kandemir. VLSI Design, page 248-253. IEEE Computer Society, (2001)

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Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip.

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Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip.