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Disambiguation of "Anders, Mark A."

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Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators.

, , , , and . ARITH, page 84-87. IEEE, (2019)

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Dr. -Ing. Daniel Markthaler University of Stuttgart

Replication Data for: Biocatalytic stereocontrolled head-to-tail cyclizations of unbiased terpenes as a tool in chemoenzymatic synthesis, and . Dataset, (2024)Related to: Schneider, Andreas; Lystbæk, Thomas B.; Markthaler, Daniel; Hansen, Niels; Hauer, Bernhard (2024): Biocatalytic stereocontrolled head-to-tail cyclizations of unbiased terpenes as a tool in chemoenzymatic synthesis. In: Nature Communications, 15, 4925. doi: 10.1038/s41467-024-48993-9.

A. Laukemann

Mark Burkhardt University of Stuttgart

Dr. Mark Hamilton University of Stuttgart

Mark Kurcsics University of Stuttgart

 

Other publications of authors with the same name

A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 50 (1): 59-67 (2015)A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 52 (4): 940-949 (2017)A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 41 (1): 256-264 (2006)25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS., , , , , , , , , and 4 other author(s). ISSCC, page 392-394. IEEE, (2020)A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS., , , , , , , and . ISSCC, page 182-184. IEEE, (2012)16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS., , , , , , , , , and . ISSCC, page 278-279. IEEE, (2014)A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS., , , , and . ISSCC, page 256-600. IEEE, (2007)An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS., , , , , and . ISSCC, page 1785-1797. IEEE, (2006)A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS., , , , and . ESSCIRC, page 182-185. IEEE, (2008)34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms., , , , , , , , , and . ESSCIRC, page 90-93. IEEE, (2018)