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Disambiguation of "Mathew, Sanu K."

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A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS.

, , , , , , and . IEEE J. Solid State Circuits, 41 (1): 256-264 (2006)

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K. Stahl

K. Gaiser

K. Lindow

Grzegorz K. Karch

Ranjith Mathew Roy University of Stuttgart

 

Other publications of authors with the same name

A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 55 (4): 945-955 (2020)16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS., , , , , , , , , and . ISSCC, page 276-277. IEEE, (2014)A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 56 (4): 1141-1151 (2021)An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 54 (4): 1074-1085 (2019)A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 44 (1): 107-114 (2009)A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit., , , , , , , and . IEEE J. Solid State Circuits, 42 (1): 26-37 (2007)Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator., , , , , and . J. Solid-State Circuits, 53 (8): 2399-2414 (2018)µRNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 51 (7): 1695-1704 (2016)25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range., , , , , , , , , and 4 other author(s). ISSCC, page 396-398. IEEE, (2020)A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 41 (1): 256-264 (2006)