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Disambiguation of "Krishnamurthy, Ram K."

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16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS.

, , , , , , , , , and . ISSCC, page 276-277. IEEE, (2014)

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K. Stahl

K. Gaiser

K. Lindow

Roman Ramminger University of Stuttgart

Astrid Yuliana Ramírez Hernández University of Stuttgart

 

Other publications of authors with the same name

Holistic handwritten word recognition using temporal features derived from off-line images., and . Pattern Recognition Letters, 17 (5): 537-540 (1996)A CMOS wave-pipelined image processor for real-time morphology ., and . ICCD, page 638-643. IEEE Computer Society, (1995)A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS., , , , and . VLSI Circuits, page 255-256. IEEE, (2018)µRNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 51 (7): 1695-1704 (2016)Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections., , , and . Low Power Networks-on-Chip, Springer, (2011)25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range., , , , , , , , , and 4 other author(s). ISSCC, page 396-398. IEEE, (2020)Exploring the design space of mixed swing quadrail for low-power digital circuits., and . IEEE Trans. VLSI Syst., 5 (4): 388-400 (1997)A leakage-tolerant low-leakage register file with conditional sleep transistor., , and . SoCC, page 241-244. IEEE, (2004)A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS., , , , , , , , , and 1 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS., , , , , , , , , and . ISSCC, page 276-277. IEEE, (2014)