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Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles., , , , and . VLSI-SoC, volume 240 of IFIP, page 267-281. Springer, (2005)Failure Analysis and Test Solutions for Low-Power SRAMs., , , , , , , and . Asian Test Symposium, page 459-460. IEEE Computer Society, (2011)Comprehensive bridging fault diagnosis based on the SLAT paradigm., , , , , , , and . DDECS, page 264-269. IEEE Computer Society, (2009)On Using Efficient Test Sequences for BIST., , , , and . VTS, page 145-152. IEEE Computer Society, (2002)Advanced test methods for SRAMs., , , , and . VTS, page 300-301. IEEE Computer Society, (2012)Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs., , , , , and . VTS, page 361-368. IEEE Computer Society, (2007)Impact of resistive-open defects on the heat current of TAS-MRAM architectures., , , , , , , , and . DATE, page 532-537. IEEE, (2012)A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction., , , , , , , , and . European Test Symposium, page 81-86. IEEE Computer Society, (2010)Random Adjacent Sequences: An Efficient Solution for Logic BIST., , , , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 413-424. Kluwer, (2001)Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization., , , , and . European Test Symposium, page 116-121. IEEE Computer Society, (2005)